(a) Field of the Invention
The present invention relates to a method for manufacturing a silicon bonded wafer and, more particularly, to a method for manufacturing a silicon bonded wafer used for fabricating a composite semiconductor device including a power transistor element and control circuit elements.
(b) Description of the Related Art
A composite semiconductor device is known in which a power transistor element having a high breakdown voltage and called a vertical transistor and control circuit elements called lateral transistors are provided on a common semiconductor substrate. In a composite semiconductor device, a current path of the power transistor is formed from the top surface to the bottom surface of the semiconductor substrate and it is particularly important to provide a satisfactory separation between a vertical element forming region for receiving the power transistor and a lateral element forming region (or control circuit forming region) for receiving the control circuit(s). A silicon bonded wafer has been proposed to meet such a requirement. For example, in the silicon bonded wafer disclosed in Patent Publication No. JP-A-4(1992)-29353, the lateral element forming region has an SOI structure.
The conventional method for manufacturing a silicon bonded wafer described in the publication as mentioned above is shown in FIGS. 1A through 1E.
A first substrate 311 made of a heavily doped N-type monocrystalline silicon is prepared. The first substrate 311 has a main surface 312 oriented in a lattice plane (100). A flat recess 314 is formed by, for example, a reactive ion etching (RIE) process in an area corresponding to a lateral element forming region for receiving control circuit. An insulating film 315 is formed over the main surface 312 including the surface of the flat recess 314, as shown in FIG. 1A. Subsequently, at least the insulating film 315 is ground and polished to leave a portion of the insulating film 315a filling the flat recess 314 and having a top surface flush with the main surface 312 of the power element forming region, as shown in FIG. 1B. A second substrate 301 made of, for example, a lightly doped N-type monocrystalline silicon is prepared which has a main surface 302 oriented in a lattice plane (100). The first and the second substrates 311 and 301 are coupled to each other such that the main surface 312 of the first substrate 311 meets the main surface 302 of the second substrate 301, with the crystal axes thereof coinciding with each other. The first and second substrates 311 and 301 are then subjected to a heat treatment to bond the first substrate 301 and the second substrate 311 together, as shown in FIG. 1C.
Next, the second substrate 301 is ground and polished at the side of the second surface thereof opposing the main surface 302 of the second substrate 301 to obtain a predetermined thickness of the second substrate 301. Subsequently, an insulating film 303 is formed over the entire polished surface of the second substrate 301. The insulating film 303 is made of a material having an etch rate different from that of the insulating film 315a. The insulating film 303 is then subjected to a patterning process. Then, an anisotropic wet etching process is performed by using the patterned insulating film 303 as a mask to form separating grooves 304 (V-grooves) each having a V-shaped cross section and reaching the surface of the insulating film 315a. By formation of the V-grooves 304, the second substrate 301 is divided into a vertical element forming region 301a and a plurality of lateral element forming regions 301b, as shown in FIG. 1D. Subsequently, the insulating film 303 is removed, following which another insulating film 305 is formed as covering the entire surface including the surfaces of the V-grooves 304 and the polished surfaces of the vertical element forming region 301a and the lateral element forming regions 301b, as shown in FIG. 1E.
Next, a polycrystalline silicon film 306 having a thickness greater than the depth of the V-grooves 304 (i.e., the thickness of the lateral element forming regions 301b) is formed to cover the vertical element forming region 301a, the lateral element forming regions 301b and the V-grooves 304, as shown in FIG. 1F. Subsequently, the polycrystalline silicon film 306 and the insulating film 305 are ground and polished to expose the top silicon surfaces of the vertical element forming region 301a and lateral element forming regions 301b of the second substrate 301, thereby leaving portions of the polycrystalline silicon film 306a and portions of the insulating film 305a in the V-grooves 304, as shown in FIG. 1G. As a result, separation between the vertical element forming region 301a and one of the lateral element forming regions 301b and between adjacent each two lateral element forming regions 301b is obtained in a silicon bonded wafer.
In a silicon bonded wafer, a demand for miniturization of the device dimension is increasing as in the case of other types of semiconductor devices.